\doxysubsubsubsection{SPI2 Clock Source }
\hypertarget{group___r_c_c_ex___s_p_i2___clock___source}{}\label{group___r_c_c_ex___s_p_i2___clock___source}\index{SPI2 Clock Source@{SPI2 Clock Source}}
\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\Hypertarget{group___r_c_c_ex___s_p_i2___clock___source_ga830dbbfc78600cbef232e39318c171f5}\label{group___r_c_c_ex___s_p_i2___clock___source_ga830dbbfc78600cbef232e39318c171f5} 
\#define {\bfseries RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+PLL}~RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+PLL
\item 
\Hypertarget{group___r_c_c_ex___s_p_i2___clock___source_ga70a4c3505305bafbc0550604957f8188}\label{group___r_c_c_ex___s_p_i2___clock___source_ga70a4c3505305bafbc0550604957f8188} 
\#define {\bfseries RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+PLL2}~RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+PLL2
\item 
\Hypertarget{group___r_c_c_ex___s_p_i2___clock___source_ga75d3ff0fa3815f4668aa30c00dc87924}\label{group___r_c_c_ex___s_p_i2___clock___source_ga75d3ff0fa3815f4668aa30c00dc87924} 
\#define {\bfseries RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+PLL3}~RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+PLL3
\item 
\Hypertarget{group___r_c_c_ex___s_p_i2___clock___source_ga435d41f2ee1f56c85859a1f490ba5544}\label{group___r_c_c_ex___s_p_i2___clock___source_ga435d41f2ee1f56c85859a1f490ba5544} 
\#define {\bfseries RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+PIN}~RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+PIN
\item 
\Hypertarget{group___r_c_c_ex___s_p_i2___clock___source_ga02cd3d3506659ece5c05e3b917f5dd1d}\label{group___r_c_c_ex___s_p_i2___clock___source_ga02cd3d3506659ece5c05e3b917f5dd1d} 
\#define {\bfseries RCC\+\_\+\+SPI2\+CLKSOURCE\+\_\+\+CLKP}~RCC\+\_\+\+SPI123\+CLKSOURCE\+\_\+\+CLKP
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}
